发明名称 PARALLEL INTERPOLATION DPCM CODING CIRCUIT
摘要 <p>PURPOSE:To apply high speed interpolation DPCM coding with a low speed element by expanding an input signal into m-phase and applying forecast coding at each phase from the input signal and the result of operation from a predetermined other phase. CONSTITUTION:The input signal is split into 4-phase, and each is fed to one sample delay elements 111-114, 121-124 via delay elements 101-104 respectively the coding point signal of the own phase is generated from the one-sample delay elements 111-114, the value of the left side of the own phase is generated from the delay elements 101-104 and the value of the right side of the own phase is generated from the one-sample delay elements 121-124 to send the coding point signal of the own phase to the other phase and a forecast error signal of the own phase is extracted from subtractors 151-154. In this case, signals from other phases are given to adders 131-134. Since the forecast error signal of each phase is outputted in parallel at each coding point of time, the interpolation DPCM coding for a high speed picture signal is attained.</p>
申请公布号 JPS6251829(A) 申请公布日期 1987.03.06
申请号 JP19850191311 申请日期 1985.08.30
申请人 FUJITSU LTD 发明人 OKAZAKI TAKESHI;MATSUDA KIICHI;TSUDA TOSHITAKA
分类号 H03M7/36;H03M7/38;H04N1/417;H04N19/50 主分类号 H03M7/36
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