| 摘要 |
<p>PURPOSE:To obtain a low-priced correction clock generator circuit by providing a means executing plural frequency division made of at least two frequency division of the 2nd reference clock from the initial rise after a semi-clock frequency elapses from a detection timing at a specific logical level. CONSTITUTION:When a NAND between the output Q' of a flip-flop (FEP)1 and the two-fold clock 6 from a generating source 24 is NANDed by a NAND gate 4 to input an output 8 being the result to an FFP2, the output Q' of the FFP2 is kept H in synchronization with the 1st rise R1 of the output 8. A NAND between the output Q' of the FEP2 and the output 8 of the NAND gate 8 is NANDed by a NAND gate 5 to input the output 9 to an FFP3, an output which synchronizes with the output 9 as the Q output 10 of the FFP3 and is obtained from two-frequency division of the two-fold clock 6 can be obtained as a correction clock in synchronization with a bit data 7. Accordingly, the correction clock in synchronization with output bit data can be automatically outputted, and can sufficiently cope with the variance of timing of the output bit data due to a change in temperature, etc.</p> |
