Digital superimposed edge generation apparatus

摘要

PCT No. PCT/JP83/00204 Sec. 371 Date Apr. 3, 1984 Sec. 102(e) Date Apr. 3, 1984 PCT Filed Jun. 24, 1983.A vertical edge width calculation circuit 31 has a plurality of series-connected delay circuits 31a to 31h each having a one-horizontal period delay time. A horizontal edge width calculation circuit has a plurality of 1-pixel delay circuits 32a to 32h corresponding to the edge width. A horizontal distance between an input digital superimpose key signal and a raster position is calculated in accordance with the calculated vertical distance, that is, the edge width. In accordance with the calculated vertical and horizontal distances, a detection circuit 34 detects as a true Euclidean distance a minimum value among a plurality of Euclidean distances between the digital superimpose key signal and the raster position which are stored in ROMs 330 to 335.