| 摘要 |
A single-ended, bandpass, two stage monolithic (integrated) medium power amplifier is disclosed. The first stage of the amplifier includes a field effect transistor (FET) amplifier having a gate width of about 900 microns and the second stage a "split" field effect transistor (FET), i.e. two parallel connected FETs having gate widths of about 600 microns. The amplifiers of both stages have symmetrical biasing circuits providing the option of biasing the power amplifier from either side of the chip. The "split" (1200 micron) FET of the second stage decreases source inductance and reduces the thermal impedance.
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