| 摘要 |
PURPOSE:To obtain the correct result of totalization despite an overflow produced while the totalization is carried out in the number of times corresponding to the bit length of a counting means, by using an overflow detecting means which detects the overflow of an n-bit addition means and produces the detecting signal and a counting means which changes its count value in response to the detecting signal. CONSTITUTION:A full adder circuit 1 adds the input data X with output data A of a register 3. If an overflow is produced under such conditions, the output +OVF or -OVF of an overflow detecting circuit 2 becomes active. A clock CLK is produced at a time point when the outputs of the circuits 1 and 2 are stabilized after the data X is supplied to the circuit 1. As a result, the output data F of the circuit 1 is stored in the register 3 and at the same time the count value of an up-down counter 6 is changed in accordance with the state of the outputs +OVF and -OVF of the circuit 2. |
