发明名称 SYNCHRONIZATION DECISION SYSTEM
摘要 <p>PURPOSE:To perform communication with the same transmission rate as a transmission signal even when the signal is enciphered by providing a synchronization supervisory decision means to supervise the number of data bits between identification bits of a signal encoded on the reception-side and by making said number integer-times of a predetermined bit number. CONSTITUTION:A reception signal 120 is inputted to a frame pattern detecting circuit 11 and a frame-interval-bit counter 12. The circuit 11 detects the identification bit positioned before the data bits and that positioned after the data bits, and transmits a trigger signal 121 to the counter 12 and a decision circuit 13. The counter 12 counts the number N of the data bits between said two identification bits, and outputs it to the decision circuit 13. The decision circuit 13 outputs a normal pulse signal 122 to a normal pulse counter 14 when the number N of the counted data bits is a number integer-times of the prescribed number of bits. When said number is otherwise, the circuit 13 outputs an abnormal pulse signal 123 to an abnormal pulse counter 15.</p>
申请公布号 JPS627240(A) 申请公布日期 1987.01.14
申请号 JP19850147258 申请日期 1985.07.03
申请人 NEC CORP 发明人 AOYANAGI HIDEHITO
分类号 H04L7/00;H04L9/06;H04L9/12;H04L9/14 主分类号 H04L7/00
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