发明名称 COMPLEMENTARY SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
摘要 PURPOSE:To reduce a parasitic MOS inversion leakage by providing a gate electrode formed through source and drain regions formed on a substrate surrounded by an element separating region and on the surface of a well element region, a high density impurity layer and a gate oxide film. CONSTITUTION:A P-well 22 is formed on the surface of an N-type silicon substrate 21, and N<+> type source and drain regions 29, 30 are formed on the well 22 element region. A parasitic leakage preventing P<+> type region 33 is formed to the place where it is suitably separated from a boundary of the source and drain regions 29, 30 near the edge of the field oxide film 23 of the element region, and a gate electrode 27 is formed through a gate oxide film 24 on the element region. Since the region 33 is not extended underneath the film 23, the region 33 is not formed before the field oxidation to reduce the number of steps and to avoid the contamination of a field oxide furnace. The parasitic MOS inversion leakage current can be prevented due to the presence of the region 33.
申请公布号 JPS627148(A) 申请公布日期 1987.01.14
申请号 JP19850144569 申请日期 1985.07.03
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 NARUGE KIYOMI
分类号 H01L27/08;H01L27/092;H01L29/78 主分类号 H01L27/08
代理机构 代理人
主权项
地址