发明名称 RISE PROCESSING METHOD OF PROCESSOR
摘要 PURPOSE:To restart a processing after a short down-time by adding an address partial change means, so that it can be assigned automatically to an area being different from a fault generated area at the time of ririse, when a system-down has occurred. CONSTITUTION:When 1 bit in a memory block Ma in a RAM 2 goes wrong at thetime of a through-mode, a parity error 9 is generated in a use area of a system program and a processor stops. A user tries a rerise by turning on a reset switch, and generates a reset signal 11. An address partial change part 8 is inverted and goes to an inversion mode, and the next memory block Mb is assigned to a main memory address. The block Mb can execute normally a program, reloads the program from an auxiliary storage device, and executes a user program. When a parity error signal 9 is generated, the processor inhibits to use its page of the block Ma, secures a new page, executes reloading to the new page from the auxiliary storage device as necessary, and executes a processing so that it can be continued.
申请公布号 JPS622339(A) 申请公布日期 1987.01.08
申请号 JP19850140485 申请日期 1985.06.28
申请人 HITACHI LTD 发明人 MIYAZAKI YOSHIHIRO;TANJI MASAYUKI;NISHIKAWA ATSUHIKO;TAKATANI SOICHI
分类号 G06F9/445;G06F9/06;G06F12/16 主分类号 G06F9/445
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