| 摘要 |
PURPOSE:To switch each mode to a different mode on the basis of signal input from the external by forming two operation modes, i.e. operation stop and operation permission modes, in a watchdog timer. CONSTITUTION:When a power source is turned on, a reset signal 4 is turned to a high level for a fixed period and an FF 40 turns an operation permission flag 18 to a low level. Thereby, a clock signal 6 is interrupted by an AND gate, a free run counter input clock signal 17 is turned to a low level, a free run counter 9 stops counting, and the watchdog timer stops its operation. When a processor executes writing of data in a specific address, a specific address from an address bus 3 is decoded by a decoder 11, AND between the decoded address and a write signal 5 is found out and a signal 13 is turned to a high level. Since the signal 4 has been turned to the low level at that time, the FF 40 is inverted, the permission flag 18 is turned to the high level, the clock signal 6 is passed through a gate 16 and inputted to the free run counter 9 as the free run counter input clock signal 17.
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