| 摘要 |
PURPOSE:To simplify a circuit pattern, and to improve the degree of integration by forming P channel and N channel elements constituting a CMOS circuit by using a slender linear polysilicon layer. CONSTITUTION:An insulating film 21 consisting of silicon dioxide is shaped to the upper surface of a semiconductor substrate 20 composed of an silicon substrate, and several element Q1, Q2 and Q3 is formed by employing a slender linear polysilicon layer 22 shaped onto the insulating film 21. An impurity is doped selectively into the silicon layer 22, thus forming P-type regions 31a, 31b:32a, 32b and N-type regions 33a, 33b shaping respective source and drain region. Insulating layers 23 onto the upper surface of the polysilicon layer 22 and gates 24 consisting of polysilicon to which the impurity is doped are formed, thus constituting P channel MOSFETs Q1, Q2 and an N channel MOSFET Q3. Accordingly, there is no possibility of a latch-up because the elements are isolated from the semiconductor substrate 20 by several element insulating film 21, and areas required for element isolation are also reduced because the elements are isolated by high resistance sections (i) in the polysilicon layer 22. |
