发明名称 MICROCOMPUTER
摘要 PURPOSE:To reduce an area occupied by a data bus on a chip at forming a microcomputer of an integrated circuit by setting up the number of constitutional bits of the data bus less than that of an address data and using 2 machine cycles or more to execute a call instruction or an interruption. CONSTITUTION:The number of constitutional bits of the bus line for transferring return address data formed by an incrementer 12 at the execution of a call instruction in a subroutine to a stack area 16 formed in a general memory is set up less than the number of bits of a program register and >=2 machine cycles are used to execute the call instruction. Gate circuits 21-23 send the output of the high-order bit (or low-order bit) of the incrementer 12 to the data bus in the 1st machine cycle and gate circuits 19, 20 send the output of the low-order bit (or high-order bit) of an address latch 13 for storing a return address outputted from the incrementer 12 to the data bus 14 in the 2nd machine cycle. The return address data are divided and stored in the stack area 16.
申请公布号 JPS61289430(A) 申请公布日期 1986.12.19
申请号 JP19850132157 申请日期 1985.06.18
申请人 SANYO ELECTRIC CO LTD 发明人 TSUKAGOSHI MASAAKI
分类号 G06F9/42 主分类号 G06F9/42
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