| 摘要 |
PURPOSE:To attain a parallel processing and to reduce loss time required for reading data by generating a timing pulse for driving an address specifying circuit and a data register on the basis of a reference clock in common with a host device. CONSTITUTION:After an enable signal S5 is outputted from the 2nd decoder 25 of a timing circuit 6, the pattern data D of 1 byte are read out from a ROM of which reading address is specified. After the output of the enable signal S5, the pattern data D are latched by host and lower data registers 16, 17 respectively on the basis of latch signals S8, S9 outputted from the 2nd decoder 25, read out in accordance with reading command signals C3, C4 supplied through the 1st decoder 11 and supplied to an MPU which is a host device. The pattern data D at every 2 bytes can be sequentially read out from the ROM on the basis of the command outputted from the MPU, so that parallel processing can be attained.
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