发明名称 PULSE PEAK HOLDING CIRCUIT
摘要 PURPOSE:To obtain an output at the same response speed as an input pulse period by holding alternately the peak values of respective periodically inputted pulses by a pair of holding circuits and switching alternately the held values to output them. CONSTITUTION:When a pulse is inputted to an input terminal In, the initial pulse makes a capacitor C2 electrically charged and a capacitor C1 discharged, so that an analog switch SW2 is turned on and the holding value of the capacitor C2 is outputted to an output terminal Out. When the 2nd pulse is inputted, a transistor TR2 is turned on and a transistor TR1 is turned off, so that the capacitor C1 is charged up to the peak value of the pulse. Since the analog switch SW1 is turned on at that time, the holding value of the capacitor C1 is outputted.
申请公布号 JPS61278979(A) 申请公布日期 1986.12.09
申请号 JP19850119487 申请日期 1985.06.01
申请人 AKAI ELECTRIC CO LTD 发明人 MATSUNAGA TAKAYUKI
分类号 H03K5/1532;G06G7/12;G06G7/25;H03K6/00 主分类号 H03K5/1532
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