发明名称 MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To efficiently reduce an over head of an access to a shared memory from respective microprocessors by fetching the data in the shared memory while operating by a program in an internal memory and communicating with other processor and carrying out a processing or the like such as a calculation and an output processing. CONSTITUTION:A microprocessor 1 outputs an address and the data on a local bus 13 in order to write the data to a shared memory 11 and a bus control circuit 3 holds the address in an address holding circuit 6 and the data in a write data holding circuit 5. The microprocessor 1 terminates a bus cycle and moves to a next operation. The bus control circuit 3 obtains an using right of a system bus 12 and outputs the address held in the address holding circuit 6 and the data held in the write data holding circuit 5 to a system data bus 17. The shared memory 11 receives the address and then writes the data in a relevant address of the shared memory 11 and returns a SACK 20.
申请公布号 JPS61275966(A) 申请公布日期 1986.12.06
申请号 JP19850117586 申请日期 1985.05.30
申请人 HITACHI LTD 发明人 TANAKA HIROYUKI
分类号 G06F15/16;G06F12/00;G06F13/18;G06F15/173;G06F15/177 主分类号 G06F15/16
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