| 摘要 |
PURPOSE:To ensure the stable demodulation despite of a duty change of a modulated signal by using a clock having a rise in a high level period of the modulated signal to demodulate the data signal. CONSTITUTION:For a synchronizing signal consisting of logical value ''1010'', the rise part exists with only two signals shown by B with double period as much as a rise edge signal (c), i.e., a signal A obtained from an ample signal. However the 3rd counter 8 is constituted so as to be reset automatically when it counts the reference pulse signals (b) having a frequency 20 times as much as the ample signal up to 20. Therefore the counter 8 is resetin a cycle approximately equal to a reset signal (e) consisting of the signal (c). Thus, a demodulated signal (i) is obtained from a demodulating clock signal (h) produced in a period of the synchronizing signal. |
