发明名称 CMOS MICROPROCESSOR ARCHITECTURE
摘要 A CMOS microprocessor is provided having a plurality of registers wherein the registers contain RAM type storage cells resulting in compact, fully static registers. In most cases the registers are connected to two buses. A 5 bit temporary register and an 8 bit program counter are each connected to three buses. An incrementer can provide an increment or decrement function but cannot be used to store functions. A bit code generator is connected to a data bus thereby allowing any one selected data bit carried by the data bus to be modified. A 5 bit high order program counter is capable of directly transferring its contents to the 5 bit temporary register. An 8 bit low order incrementer is capable of incrementing three different registers which are an address storage register, a program counter, and a stack pointer. A 5 bit high order incrementer is also capable of incrementing three registers which are an address storage register, a program counter, and a temporary register. An ALU has a first and a second input, which because of the bus structure used, can both receive data simultaneously.
申请公布号 DE3071812(D1) 申请公布日期 1986.12.04
申请号 DE19803071812 申请日期 1980.08.07
申请人 MOTOROLA, INC. 发明人 RAGHUNATHAN, KUPPUSWAMY;SMITH, PHILIP SOMERSET
分类号 G06F9/30;G06F9/32;G06F15/02;G06F15/78;(IPC1-7):G06F9/06 主分类号 G06F9/30
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