| 摘要 |
PURPOSE:To attain the small scale of a circuit by using an isolated point eliminating circuit comprising three 2-input NAND gates and one 3-input NAND gate so as to eliminate the isolation of a sampling value thereby eliminating chattering. CONSTITUTION:The outputs of the 1st, 2nd and 3rd 2-input NAND gates 13a, 13b and 13c are connected respectively to the 1st, 2nd and 3rd input of a 3-input NAND gate 14 and the thre 2-input NAND gates 13a, 13b and 13c and the one 3-input NAND gate 14 constitute the isolated point elimination circuit for three sampling values generated at the output of a variable length shift register 7a, 7b, 7c. Thus, a signal having a level having majority among the 3 sampling values is outputted through a lien 15. That is, a signal excluding chattering from the output signal is outputted from a signal generation source 1. |
