发明名称 DECODER CIRCUIT OF SEMICONDUCTOR STORAGE DEVICE
摘要 PURPOSE:To make compact a decoder circuit and to improve an integration by disposing a power source control circuit of a logical gate generating a selecting signal according to an address signal outside a decoder. CONSTITUTION:A transistor TrQ11 of a power source control circuit 11 make a control signal -phi a gate input, connects a drain to a high potential Vcc, and a source is connected to a drain of an output node N3 and a TrQ12, and a control signal phi is inputted to a gate of the TrQ12. In a word, making all decoder output H, a line all selecting mode, if the signal phi=H, the TrQ12 is turned on, a potential of a connecting node maling the signal phi=L a gate input is lowered and a voltage of the output node N3 of the circuit 11 is lowered to OV. Accordingly, an input N1 of a CMOS inverter and the output node N3 of a NAND gate of all decoder circuits goes to L and a voltage of an output terminal 15 goes to H. Thereby, the decoder circuit can be made compact and an integration can be improved.
申请公布号 JPS61265794(A) 申请公布日期 1986.11.25
申请号 JP19850107826 申请日期 1985.05.20
申请人 FUJITSU LTD 发明人 YOSHIDA MASANOBU
分类号 H03M7/00;G11C8/10;G11C11/407;G11C11/413;G11C16/08 主分类号 H03M7/00
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