发明名称 PRECEDING DATA HOLDING DEVICE
摘要 PURPOSE:To hold preceding data successively by adding one address to an address signal from a processor and sending to a memory, and at the same time, holding the data from the memory once, and making selective output by a comparative output of an addition output and an address designation signal. CONSTITUTION:An address designation signal to which one address is added by an adder is given to a memory. Responding to this, the preceding data of the next address is sent out from the memory and held by two holding circuits according to transition of operation. When the output of the adder coincides with the address designation signal, the content of holding of each holding circuit is selected by a switching device by the output of a comparator, and the data corresponding to the value of the address designation signal being sent by a processor are given to the processor. In the case where the processor executes an instruction etc. in the memory, the address is advanced successively. Accordingly, the data of preceding address are held at all times, and the access time of the memory looked from the processor is shortened.
申请公布号 JPS61262859(A) 申请公布日期 1986.11.20
申请号 JP19850102561 申请日期 1985.05.16
申请人 YAMATAKE HONEYWELL CO LTD 发明人 ISHIKAWA TERUO
分类号 G06F12/08;G06F12/00;G06F12/02 主分类号 G06F12/08
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