| 摘要 |
<p>An instruction processor effecting operations for register operands and for processing branch instructions to perform address calculations for branch destination instructions, comprising general-purpose registers (11) storing data including results of operations of said instruction processor, address adders (114, 115) calculating the address of branch destination instructions by using data read out from the general-purpose register and an ALU (114) performing arithmetical or logical operations on the data read out from the general-purpose register in the decode cycle of the instructions, whereby the result of the arithmetical or logical operation is inputted in the address adder instead of input from the general-purpose register, in the case where the result of the arithmetical or logical operations is utilized for address calculation in the execution of a succeeding instruction.</p> |
