| 摘要 |
A bit-decision circuit or slicer for a digital communications receiver includes a first comparator which compares the received signal level with a reference slicing level. In order to have the lowest error rate, the reference slicing level must be controlled. Control is provided by periodic level indicating pulses in the transmitted signal. The level indicating pulses have predetermined nominal duration and controlled rise and fall times. A pulse width locked loop at the receiver responds to the level indicating pulse at the output of the comparator. The pulse width locked loop includes a start-stop oscillator which produces an odd or an even number of oscillations in response to each level-indicating pulse depending upon the ON time of the oscillator. A flip-flop coupled to the oscillator changes state during each oscillation, so that an even number of oscillations causes the flip-flop output to remain in the same state after the level indicating pulse as before, while an odd number of oscillations causes a change of state. The average D.C. level at the output of the flip-flop therefore changes significantly for a change of duration of the level indicating pulse corresponding to one clock oscillation cycle or a portion of a clock oscillator cycle. The flip-flop output level is filtered and applied as an input signal to a second comparator. The second comparator switches state in response to excursion of the filtered flip-flop signal above and below a reference level. The output of the second comparator is filtered to form the reference slicing level for the first comparator. This closes a pulse width locked loop which takes excursions between two extreme values of pulse width. The data pulses occurring in the interval between level indicating pulses are compared with the same reference level for low error rate.
|
