Data processing system having unique bus control protocol

摘要

In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.