| 摘要 |
PURPOSE:To multiply a row vector composed of two elements by a column vector at a high speed by expressing two real numbers comprising row and column vectors with the product of a mantissa part and two power, latching the mantissa part and an exponent part in a shift register and executing the prescribed arithmetic processing. CONSTITUTION:In terms of multiplying the row vector composed of two elements such as am1X2<ae1-m> and bm1X2<be1-m> by the column vector expressed in am2X2<ae2-m> and cm2X2<ce2-m>, the am1 and am2 in shift registers (SR) 11 and 19 are loaded by a multiplier 23 and the bm1 and cm2 are loaded on a multiplier 24 according to trigger pulses CLK1 and CLK2, respectively. The sum of an ae1 and ae2 and the one of a be1 and ce2 are obtained by adders 26 and 27, whichever is larger, is selected by a selector 31, and loaded on a register 34 and a control block 35. The product output of the multipliers 24 and 25 are added 25 and transmitted to the block 35. An exponent part data ae3 and a mantissa part data am3 available from the block 35 according to the trigger pulses CLK5 and CLK4 are latched by the registers 34 and 35.
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