发明名称 MEMORY ACCESS CONTROLLING SYSTEM IN MULTIPROCESSOR SYSTEM
摘要 PURPOSE:To make efficient access control by comparing an ID of access requesting unit and an ID of access requesting unit selected directly before in other system when an access request is selected by priority control of a memory controller of own system, and suppressing the memory access of own system when they coincide. CONSTITUTION:Priority controlling circuits 16a and 17a make priority control on an access request from subsystems 10, 11 of own system and other system, and select a unit of the highest priority and output the ID, and permit access to main memories 18, 19 of own system. Comparators 16c and 17c compares the result of selection by priority control of MCU of other system 1 clock before and the result of selection by priority control of MCU of own system in the present clock. Outputs of comparators 16c and 17c are made effective only when ID outputted from priority control circuits 16a and 17a is that of own system unit, and when an effective coincidence output is generated, starting of access to the main memory of own system is suppressed in the system.
申请公布号 JPS61248153(A) 申请公布日期 1986.11.05
申请号 JP19850089769 申请日期 1985.04.25
申请人 FUJITSU LTD 发明人 TOYOKI NORIYUKI
分类号 G06F12/00;G06F9/52;G06F13/18;G06F15/16;G06F15/177 主分类号 G06F12/00
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