| 摘要 |
<p>PURPOSE:To attain the weight state detection of each processor and the next step start control through one signal line by connecting plural processors executing the prescribed processing independently and a control part controlling each processor in terms of wired logic. CONSTITUTION:A delayed synchronizing signal oscillator circuit DL 4 installed on the control part 3 and respective processors 1-1-1-n are controlled through the signal line 2 connected by wired logical elements U1 and U2. When a wait instruction is executed, each flip-flop FF 2 is set to open the output of the element U2, because each processor is synchronous. When all elements U2 connected to the signals line 2 are opened, the FF 1 of the control part 3 is set, and the signal line 2 comes to L level through an AND gate G1 and the element U1. The the FF 3 of each processor is set, and the DL 4 is operated after the prescribed time. Then the FF 4 is set through the gate G1, the signal line 2 and the gate G2 to start the next step.</p> |
