发明名称 ADDITION CIRCUIT
摘要 PURPOSE:To produce a carry signal at high speed by using only the composite circuit of a 2-input AND circuit, a 2-input OR circuit, 2-input AND, a 1-input NOR, a 2-input NOR and 1-input AND and an inverter to form a carry foresight addition part. CONSTITUTION:The binary numbers a4-a1 and b4-b1 are added by a logic circuit consisting of a 2-input NAMD circuit, a 2-input OR circuit and an inverter. Then addition values G4-G1 and P4-P1 are delivered. Based on these addition values and the carry input Cin, the addition is carried out by a composite circuit of a 2-input AND, a 1-input NOR composite circuit, a 2-input NAND circuit, an inverter and a 2-input NOR-1-input NAND composite circuit and a logic circuit containing an inverter, a 2-input NAND circuit and a 2-input NOR circuit connected in a binary tree form. Then the result signals S4-S1 and the carry output Cout to be given to an upper digit are calculated. Thus a high-speed arithmetic operation is possible with this addition circuit since two transistors are connected in series between the output and a power supply.
申请公布号 JPS61240330(A) 申请公布日期 1986.10.25
申请号 JP19850081254 申请日期 1985.04.18
申请人 TOSHIBA CORP 发明人 HORI CHIKAHIRO
分类号 G06F7/50;G06F7/507;G06F7/508 主分类号 G06F7/50
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