| 摘要 |
PURPOSE:To achieve a higher fault detection rate, by inputting a clock of a testing circuit such as FF through a clock switching circuit to prevent the generation of racing. CONSTITUTION:A clock switching circuit 2 and a test clock terminal 1 are provided and a pulse signal is designated to be inputted from a clock terminal 1 by ATG (automatic test generation). The ATG keeps other data from changing simultaneously when a clock signal is outputted as pulse signal thereby making the output from a logical circuit 4 constant. Thus, there is no racing generated. On the other hand, an observation terminal 3 for testing is provided to avoid a drop in the fault detection rate otherwise caused by the use of the clock switching circuit 2 which may block the route of discovering a fault of a logical circuit 4. The arrangement of the terminal 3 can elevate the fault detection rate. |
