| 摘要 |
PURPOSE:To make quickly a pair of digit lines into the same potential without delaying the occurrence of a one-shot signal by providing an EQ signal generating circuit which generates an EQ signal at an output level more than a power source potential VCC in synchronizing with the transition of an input address signal. CONSTITUTION:While an input address signal will not transit because of a read state, a bootstrap capacity C is always precharged at a level potential available from subtracting the threshold voltage VT of a charging transistor Q4 from the power source potential VCC. Here, when the address input signal transits, the level inversion buffer output OS' of the one-shot signal-OS is added to the bootstrap capacity C by delaying slightly an address transitting time, and the EQ signal exceeding the power source potential VCC is applied to the gate of an EQ transistor Q3 through the EQ signal. Thus the EQ transistor Q3 is conducted almost the same time as the one-shot signal -OS, whereby a pair of digit lines D and -D can be quickly made into the same potential. |
