| 摘要 |
PURPOSE:To compare the phase between signals correctly even with the presence of the change in the operating condition and variance in the characteristic by controlling the delay time of a delay element of a control delay circuit and a comparison delay circuit based on the output of a control latch circuit. CONSTITUTION:A delay circuit 13 consists of the same delay elements as those for a delay circuit 12, and when the delay time is controlled correctly, an output of a delay element 14N is delayed by one period of a signal B. Output signals QA, QB of latches 16, 18 are respectively logical '0', '1' when they are controlled. When the delay time is too long, the signals QA, QB are respectively logical '1'. When the delay time is too short, the signals QA, QB are respectively logical '0'. A control signal generating circuit 20 generates a control signal based on the output signals QA, QB and outputs it to delay elements 121-12N, 141-14N. Thus, accurate phase comparison is attained by using the output signal of the delay elements 121-12N. |
