| 摘要 |
<p>PURPOSE:To obtain a stable internal clock signal even if power source noise takes place by providing a gate controlled by an internal clock signal control means, an internal clock signal generating means, a frequency detecting means for an external clock signal and a phase detecting means. CONSTITUTION:The frequency detection circuit 62 detects the frequency of the external clock signal T for synchronization from a power supply synchronization circuit 5 and when a signal T entering the phase detection circuit 63 is within the range of phase error, the circuit 63 detects the phase of the signal T. A control circuit 64 initializes the internal clock signal CLK generated in the internal clock signal generating circuit 65 by using the phase and frequency detected in this way. The control circuit 64 controls the input of the signal T to a gate 61 by using the signal CLK. When the signal T is inputted, the gate 61 is opened only within a permissible error range for the expected time. Even when the gate 61 is closed and the signal T is inputted to the gate 61 due to noise, its input is neglected and the signal CLK is held.</p> |
