发明名称 CMOS SEMICONDUCTOR DEVICE
摘要 PURPOSE:To improve the resistance to latch-up by providing a guard ring which is formed in a reverse conductivity type at least either on the semiconductor device side near the boundary between a semiconductor device and a first region, or on the first region side, and on which a prescribed bias is impressed through a resistor. CONSTITUTION:The base of an N-P-N transistor 45 is connected to the base of an N-P-N transistor 31 through the intermediary of the base series resistance 43 of the N-P-N transistor 45, and the base of the N-P-N transistor 31 is connected to a Vss terminal 49 through the intermediary of a parasitic substrate resistance 35, while the emitter of the N-P-N transistor 31 is connected directly to the Vss terminal 49. When a current flows out from a terminal A due to noise or the like from the outside, in a circuit construction as described above, the collector current of the N-P-N transistor 45 turns to be the base current of an N-P-N transistor 71, and it can not drive a P-N-P transistor 29 whose emitter series resistance is small enough to supply a current necessary for causing latch-up, the thus the resistance to latch-up can be enhanced.
申请公布号 JPS61208863(A) 申请公布日期 1986.09.17
申请号 JP19850049359 申请日期 1985.03.14
申请人 TOSHIBA CORP 发明人 NIITSU YOICHIRO
分类号 H01L27/08;H01L21/82;H01L21/822;H01L27/04;H01L27/092 主分类号 H01L27/08
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