| 摘要 |
A frequency synthesizer produces a variable frequency output using a controllable oscillator and a variable frequency divider which form part of a phase locked loop. The integer division ratio of the divider can be altered during a division cycle to simulate a fractional divisor value. The phase noise or jitter which is caused by the step change in divisor value is removed by altering the divisor value in accordance with the terms of a plurality of sequences, each of which sums to zero and which represents successive rows in a Pascal's triangle. A cascaded sequence of accumulators is used to determine the starting instants of each sequence, and the length of each sequence is dependent on the number of delay lines used. Although only four accumulators are illustrated, more can be added to give any desired degree of phase noise cancellation.
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