| 摘要 |
PURPOSE:To increase a processing speed by constituting the titled device so that an address for reading out input information can be generated, when an operation code of an instruction of a sequence program is being decoded by an operation processing part. CONSTITUTION:An operation processing part 4 reads an operation code from a program memory 1, and subsequently, sends out an operation start instruction to an address generator circuit 21, and thereafter, decodes the read operation code. Also, in the address generator circuit 21, an operand and a relay number are read from a program memory 20 by the operation start instruction. Subsequently, based on its data, a table address for executing an access to a prescribed address of the input table memory to be read or written is calculated and set to an address memory. In this way, the operation of the table address can be executed by keeping pace with the decoding of the operation code, and the processing speed can be increased as a whole. |
