| 发明名称 |
|
| 摘要 |
<p>A single chip large scale integration processor possesses its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.</p> |
| 申请公布号 |
JPS6051134(B2) |
申请公布日期 |
1985.11.12 |
| 申请号 |
JP19770047511 |
申请日期 |
1977.04.26 |
| 申请人 |
INTAANASHONARU BIJINESU MASHIINZU CORP |
发明人 |
DEIRU AASAA HYUUAA;FUIRITSUPU KURISUCHAN SHUROSU;RARII RUROIDO SHUROODAA |
| 分类号 |
G06F7/38;G06F7/00;G06F7/50;G06F7/508;G06F9/22;G06F9/30;G06F12/00;G06F12/06;G06F15/16;G06F15/177;G06F15/78 |
主分类号 |
G06F7/38 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
|
| 地址 |
|
