| 摘要 |
A high resolution analogue to digital converter comprising a low resolution analogue to digital converter and an interpolating digital to analogue converter, the interpolating digital to analogue converter having a second order digital controller and a one bit quantiser arranged in a feedback loop. The low resolution analogue to digital converter is coupled to a multi-stage decimation filter having an algorithm of any stage thereof determined in dependence upon the algorithm of the immediately preceding stage. |
