发明名称 VIDEO SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To stabilize the DC reproducing rate by detecting a mean video level of a video signal, multiplying an optional factor and the level together and adding the result to a pedestal period of the video signal. CONSTITUTION:The video signal IN is fed to a voltage adder circuit 33 via a capacitor 31 as one input and fed to an APL detection circuit 34. The circuit 34 detects the APL of the video signal IN at the pedestal period of the video signal IN and the voltage VAPL of the signal S1 corresponding to the detected APL is fed to a factor multiple circuit 35. The circuit 35 multiplies a factor betain response to the control voltage Vc fed to an external control terminal 36 with the voltage VAPL and the signal S2 having the attenuated betaVAPL is fed to the circuit 33 as other input. Thus, the betaVAPL is added at the pedestal period of the video signal IN in the circuit 33. The added video signal S3 is fed to a brightness amplifier circuit 38 via a contrast control circuit 37 and the DC recovery is applied and outputted from a terminal 39.
申请公布号 JPS61184056(A) 申请公布日期 1986.08.16
申请号 JP19850022950 申请日期 1985.02.08
申请人 TOSHIBA CORP 发明人 MIYASAKO YOJI
分类号 H03F3/45;H04N5/16 主分类号 H03F3/45
代理机构 代理人
主权项
地址