发明名称 FAULT DETECTING SYSTEM FOR INPUT DEVICE
摘要 PURPOSE:To detect accurately an abnormal state through a processor by discontinuing the transmission of data for a fixed period of time or longer when an input device has a fault. CONSTITUTION:When an input device 3 has a fault, a reset circuit 60 produces a reset signal 63. a fixed pulse width producing circuit 61 produces a low level pulse signal of a fixed time width, i.e., a data cut-off signal 64 after the signal 63 is supplied. No signal 64 is produced in a normal state and the transmission/ reception of data are carried out normally via a signal line 32. When the signal 63 is produced in an abnormal state, the data sent from a terminal TX1 of an LSI 33 does not emerge on the line 32 owing to an NAND element 62 and are therefore not transmitted to the side of a keyboard 16. While the signal 64 of a fixed time width is produced and therefore the data on the line 32 is kept at a high level while the signal 64 is kept at a low level and as long as no data is sent from a processing IC 30. Then no data is transmitted from the device 3.
申请公布号 JPS61180354(A) 申请公布日期 1986.08.13
申请号 JP19850019991 申请日期 1985.02.06
申请人 HITACHI LTD 发明人 NAGAOKA MASANOBU
分类号 G06F3/02;G06F13/00 主分类号 G06F3/02
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