| 摘要 |
PURPOSE:To ensure enhance density and integration by reducing the area to be occupied by power and ground lines by a method wherein at least either of the power and ground lines is built within an insulating film in an insulating- isolating region between complementary semiconductor elements serving as memory cells. CONSTITUTION:On a semiconductor substrate 1, an N-well 2, N-type field effect transistors T1, T2, T3, T4, P-type field effect transistor T5, T6 are formed. Further, metal wirings 3, 4, 5, impurity-diffused layers 6, 7, gate electrodes 8, 9, 10 are built. A ground line 11 is formed in an insulating-isolating region 12 positioned between a T3 source 15 and T5 source 16, and the ground line 11 is connected with the source 15 at a junction point 13. |
