| 摘要 |
For synchronizing the timing subsystems (48) of the modules (12) of a distributed local area network (10) to a desired degree of accuracy the Module Central Processing Unit (MCPU) (32) of each module (12) includes a digital timing subsystem (48) which, in response to the clock signals from the source thereof (44), produces a fine timing, a synchronization, and a real time timing signal. The real time timing signals occur at one second intervals. Each of the timing subsystems (48) also produces the current time in seconds, the number of fine resolution and synchronization timing signals produced since the most recently produced real time timing signal, as well as the number of fine resolution timing signals produced since the last synchronization timing signal was produced. Two of the timing subsystems (48) of the network (10) are provided with driver circuits (50) which permit them to transmit a timing frame (60) respectively over the cables (14A,14B) of the network bus (14). One of the timing subsystems is designated as the master and the other as the slave. |
