| 摘要 |
<p>PURPOSE:To eliminate an influence of a noise of a receiving signal by detecting a direction of a phase shift between an output from a majority logical circuit for outputting many levels in high and low levels of the receiving signal, and a clock signal, by a phase comparing circuit, and varying the generation of the clock signal. CONSTITUTION:For instance, a biphase code is transmitted by a length of an about 32 piece portion of a fundamental clock pulse of an oscillator 2 from a transmitting side. This code is read successively in a shift register (SR) 1 of 3 bits by said clock, and a majority logical circuit 3 sees the contents of each bit of the SR1 and outputs a level signal whose 'H' and 'L' are large. In this way, noise of a transmitting signal is eliminated. An output of the circuit 3 is provided to a terminal D of FF circuits 6, 7, and the circuits 6, 7 output a signal which is inputted to the terminal D, from a terminal Q by the timing of a timing signal ta and tb decoded an output of a variable frequency divider 4, respectively. When this output is received, a gate circuit 8 adopts its exclusive OR and switches a frequency dividing output of the circuit 4 to 31 frequency division or 33 frequency division by its output.</p> |
