| 摘要 |
To reduce the multiplication times, a digital serial multiplier operates with a high-frequency clock which is internally generated. A ring oscillator proposed as oscillator corresponds in its structure to the structure of the gates of the arithmetic and logic unit (4, 5; 4, 5, 8) and its clock frequency is adapted to the possible operating frequency of the arithmetic and logic unit (4, 5; 4, 5, 8) in such a manner that the latter is operated at the highest speed. <IMAGE> |
