| 摘要 |
PURPOSE:To lower a cost by disposing an address assignment of performing an access of peripheral input and output device on an address space of a RAM. CONSTITUTION:A control signal line CL is connected from an instruction decoder 1 to a RAM2, further branching therefrom, the control signal line CL is connected to peripheral input and output devices 31-3n. Thereby, an address assignment for performing an access of the peripheral input and output devices 31-3n is disposed on an address space of the RAM2. A control instruction of a reading and writing and the like to the RAM2 from the instruction decoder 1 is also used for the peripheral input and output devices 31-3n. A changeover of the address thereof can be performed by an address signal from an address decoder 4.
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