| 摘要 |
PURPOSE:To attain count-up or count-down sequentially for plural address registers by using an adder to modify logically an address of an address register before one address and applying it sequentially to each register. CONSTITUTION:An address modification data and a logical address from an adder 2 inputting an addend for modification and generating a logical address are inputted sequentially to plural address registers 3,4,5. Then address information of the address registers 3,4,5 is selected in the predetermined order by a selector 10 and outputs it as a memory access (f). Further, the address register selected precedingly by the selector 10 is selected by the other selector 9 at the same time and the address information (e) is fed back to a selector 6 as the address modification data. Then a required addition is executed by the adder 2 to modify the address of the register subject to feed back. The operation is executed sequentially to the registers 3,4,5 to generate continuously plural addresses thereby clearing them.
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