发明名称 ARITHMETIC PROCESSING UNIT
摘要 <p>PURPOSE:To obtain low power consumption characteristics by supplying an oscillation output selected from plural ones outputted from plural oscillating circuits to a timing generator and controlling an arithmetic unit circuit by the output of the generator. CONSTITUTION:Oscillation outputs from the oscillating circuits f1, f2 are supplied in parallel with each other to a selecting circuit 13. The circuit 13 selects and outputs any one of the oscillation outputs f1, f2 in accordance with the level of a control signal SEL. The selected oscillation output is supplied to the timing generator 14 as a reference pulse signal phi. The generator 14 generates various timing signals required for an arithmetic logical operation unit ALU, an instruction register IR, an instruction decoder ID, a memory circuit MEM, an arithmetic processing circuit 15 including an I/O circuit by a means for frequency division or the like of the signal phi. The operation of the processing unit is stopped by stopping the oscillating operation of the selected oscillating circuit.</p>
申请公布号 JPS61128312(A) 申请公布日期 1986.06.16
申请号 JP19840251119 申请日期 1984.11.28
申请人 TOSHIBA CORP 发明人 YOSHIDA HIROKI;KOBAYASHI ATSUSHI
分类号 G06F1/08;G06F1/04 主分类号 G06F1/08
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