| 摘要 |
PURPOSE:To uniform and reduce a propagation delay time by making the num ber of passing stages of a signal always one stage of a transfer gate or an inverter independently of the input state in an exclusive OR circuit. CONSTITUTION:With an input B at logical L, a MIS-FET Tp2 is turned on a Tn2 is turned off, and although a signal is inputted to an input A, since the Tn2 is turned off, the state of the Tn1 is ineffective to the output. When the input A is logical H, since the MIS-FET Tq2 is turned on, the output X is logical H, and when the input A is logical L, both the Tp1, Tn2 are turned on, since the electric charge is extracted and the output goes to L. On the other hand, when the input B is logical H, the MIS-FET Tp2 is turned off, the Tn2 is turned on, and the Tn1 acts like an inverter, and when the input A is logical H, the output X goest to L and when the input A is logical L, the output goest to H. Since the signal passes only through one stage of parallel MIS-FET Tp1, Tp2 or one stage of the Tn1 or one stage of the Tp1, the propaga tion time is decreased. |
