| 摘要 |
PURPOSE:To reduce address access time at normal time other than writing, by reducing logical amplitude of address signal by emitter follower or a level shift down means of diode, and supplying it to an address memory circuit. CONSTITUTION:Each address signal A0, A1,-A7 is supplied to an address memory circuit 6 through emitter follower Q11, Q12 as the means of level shift down, diode D11, D12, D13 and resistor R1, R2. Since the address amplitude to be inputted to the address memory circuit 6 is smaller at the time other than writing compared with the address amplitude to be inputted to an address buffer 3, the impressing of the large load of write transistor Q1 of the address memory circuit 6 to the address signal of buffer 3 is virtually prevented. In the time of writing, the potential Vp is increased from 0V to 5V, and the address amplitude to the write transistor Q1 becomes larger.
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