| 摘要 |
A gallium arsenide transistor is provided having a self-aligned base enhancement to emitter region and a method of applying metal to the emitter region. A series of steps provide an NPN structure overlying a substrate and includes an N region of aluminum gallium arsenide overlying a P base region for increasing the efficiency of the base-emitter junction by eliminating the need for a very heavily doped emitter at the surface of the chip. Two masking layers, one overlying the other, are deposited over the N emitter region and are patterned by known photoresist methods. The P base region is enhanced by implanting beryllium ions therein and partially into the N collector region. This ion implantation is blocked by the masking layers, creating a base enhancement region aligned with the emitter region. An etching process then undercuts the lower masking layer before the upper masking layer is removed. A photoresist is deposited on the surface and the lower masking layer is removed. Metal is deposited on the surface of the photoresist and the emitter region. The photoresist is then removed, thereby lifting off the metal thereon, leaving a metal contact on a portion of the emitter reigon.
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