发明名称 FEEDBACK TYPE DATA CIPHERING AND DECODING SYSTEM
摘要 PURPOSE:To attain sure ciphering and decoding by constituting the 1st circuit which ciphers even consecutive 0s and outputs '0' when 1s are consecutive as two stages with the 2nd circuit of two-stage constitution executing inverse logic to the 1st circuit. CONSTITUTION:A ciphering device consists of two stages of a circuit comprising a shift register 1a, exclusive OR circuits 2a, 3a and an inverter 4a. That is, the device is provided further with a circuit comprising a shift register 1b, exclusive OR circuits 2b, 3b and an inverter 4b. Even when 0s or 1s are consecutive in an input data A, a ciphered output data E is obtained. A decoder is constituted symmetrically to the ciphering device and consists of shift registers 5a, 5b, exclusive OR circuits 6a, 6b, 7a, 7b and inverters 8a, 8b.
申请公布号 JPS61118037(A) 申请公布日期 1986.06.05
申请号 JP19840238321 申请日期 1984.11.14
申请人 HITACHI LTD 发明人 KUSUMOTO YUICHI;KOHAMA TOSHINOBU
分类号 H04L9/06;H04L9/14;H04L9/18;(IPC1-7):H04L9/02 主分类号 H04L9/06
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