发明名称 GAAS LOGIC INTEGRATION CIRCUIT
摘要 PURPOSE:To execute the high integration with a small logical amplitude and a small noise margin by connecting a GaAs diode between a gate of a driver EFET and a signal input terminal, setting a junction capacity to 2.5 times or above of the driver EFET and composing an inverting circuit. CONSTITUTION:Between the first normally off type EFET11, driver and a signal input terminal, a GaAs Schottky diode 13 is connected. In proportion to a junction capacity of the diode 13 and a gate junction capacity of an EFET11 under the same bias conditions, the junction capacity between gate sources of EFET is generally 1/2 of the whole gate junction capacity, and when the diode having a junction area larger than 0.75 times of the gate junction area of EFET is used, the circuit is operated. Namely, the diode with the area ratio S2/S1 of 1.25 or above is used, in other words, the junction capacity of the diode is 2.5 times or above of the junction capacity between gate sources of EFET. When this is used as the design and production standard of the inverter, the inverter can be operated at a high speed.
申请公布号 JPS61116418(A) 申请公布日期 1986.06.03
申请号 JP19840235959 申请日期 1984.11.10
申请人 AGENCY OF IND SCIENCE & TECHNOL 发明人 IGAWA YASUO;HOJO AKIMICHI
分类号 H01L27/095;H01L21/8222;H01L27/082;H03K19/017;H03K19/0952 主分类号 H01L27/095
代理机构 代理人
主权项
地址