发明名称 |
MEMORY CONTROLLER |
摘要 |
PURPOSE:To decrease the number of data lines and also to attain the use of a memory with high efficiency by making use of the idle time between the input/output of the data and that of the next data for input/output of data on another dynamic RAM. CONSTITUTION:A memory controller 1 controls a memory block consisting of plural pieces of dynamic RAMs. Both address and data lines (d) and (a) are provided in common with all dynamic RAMs contained in the memory block. While control lines (b) and (c) are set independently of each other for each dynamic RAM. Then each dynamic RAM receives the time-division input/ output control by the control signals supplied via both lines (b) and (c) and via both common lines (d) and (a).
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申请公布号 |
JPS61114351(A) |
申请公布日期 |
1986.06.02 |
申请号 |
JP19840234184 |
申请日期 |
1984.11.08 |
申请人 |
HITACHI LTD;HITACHI VIDEO ENG CO LTD |
发明人 |
OSAKA ICHIRO;YOSHIDA NAOMI;AKITAKE ISAO;UEKI YUKIYA;NAKAJIMA MITSUO |
分类号 |
G11C7/00;G06F12/02;G06F12/06;G06F13/16;G11C11/401 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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